A field effect transistor (FET) using a compound semiconductor such as GaN has excellent high-frequency characteristics. Accordingly, the FET has been widely in practical use as a semiconductor device operating in a microwave band.
The FET has, for example, the following structure, as disclosed in Japanese Patent Application Laid-Open No. 2007-227885. On an operating layer formed on a semiconductor substrate, a rectangular source electrode and a rectangular drain electrode are formed, spaced from each other. Between the source electrode and the drain electrode, a band-like gate electrode is formed. On the operating layer, an insulating film is formed between the source electrode, the drain electrode and a gate electrode, respectively. A field plate electrode whose length on the source electrode side is short and whose length on the drain electrode side is long is formed on the gate electrode.
In the FET, the long field plate electrode is formed on the gate electrode on the drain electrode side. Hence, the potential at a drain side end portion of the gate electrode can be lowered. Thereby application of a high voltage to the FET is achieved. However, while the field plate electrode can lower the potential at the drain side end portion of the gate electrode as described above, an interval between the field plate electrode and the drain electrode becomes smaller, which increases the floating capacitance generated between the electrodes, and thus phenomena such as oscillation and a gain drop are likely to occur. That is, the floating capacitance is a possible cause of degradation in FET performance. Accordingly, it is very important to form the field plate electrode in such a manner as to suppress the increase in the floating capacitance.
As a method for forming a field plate electrode so as to control an increase in floating capacitance, the following method is known, as disclosed in Japanese Patent Application Laid-Open No. 10-135239. The method is for integrally forming a gate electrode and a gate field plate electrode of a semiconductor device by means of metal vapor-deposition using a resist layer having an overhang opening.
By thus performing the metal vapor deposition using a resist layer having an overhang opening, the metal vapor-deposited at the opening portion and the metal vapor-deposited on a resist layer can be spaced from each other. Hence the excessive metal vapor-deposited on the resist layer can also be removed when removing the resist layer. Accordingly, no excessive metal will remain on the field plate electrode, thus forming a field plate electrode while suppressing an increase in floating capacitance.
However, in performing metal vapor deposition using a resist layer having an overhang-shaped opening in this way, deposited metal components diagonally incident to the opening and metal deposited at the opening may flow through a gap between an end portion of the field plate electrode and a side wall of the opening in the resist layer, which generates a thin trailing portion at the end portion of the field plate electrode. Accordingly, it has conventionally been difficult to suppress an increase in floating capacitance due to the trailing portion, which causes a problem of degradation in performance of the device.